This invention relates to semiconductor devices and a fabrication method thereof, for example, to static RAMs (Random Access Memories).
Conventionally static RAMs, for example, have severe restrictions on pattern layouts, because many wirings such as ground wires and bit lines have to be passed through regions of small area. Thus, in silicon gate MOS integrated circuits, a so called "direct contact" method is generally known, in which gate electrodes are not connected to diffusion layers (sources, drains, or regions corresponding thereto) by conventional metal wiring layers such as Al or the like but are connected directly to the diffusion layers using polysilicon or the like. By using the direct contact method, pattern layouts in said static RAMs or the like is defined more freely, and the degree of integration increases, because metal wiring layers such as, for example, power source supply wires, can be disposed directly over connecting parts or the like of the gate electrodes and the diffusion layers.
However, semiconductor devices fabricated by said direct contact method have several serious problems which cannot be avoided in their processes. Hereinbelow, an example of a fabrication process of semiconductor devices by the direct contact method and its problems will be discussed in regard to FIGS. 5A to 5H. To facilitate the understanding, the figures are partly exaggerated.
First, as shown in FIG. 5A, a field oxide film 2 for element separation is grown on a P type silicon substrate 1 by a well-known LOCOS (Local Oxidation of Silicon) method, and then a gate oxide film 3 is formed by thermal oxidation.
Next, after a predetermined area is covered by, for example, a photoresist 30, as shown in FIG. 5B, the gate oxide film 3 in a predetermined area is etched away as shown in FIG. 5C (this forms a predetermined contact part 4).
Next, as shown in FIG. 5D, a polysilicon layer 5 is deposited on the entire face including the contact part 4 by a well-known CVD (Chemical Vapor Deposition) method; and the polysilicon layer 5 is doped by, for example, phosphorus or the like to be N type; and then after a predetermined area is covered by a photoresist 40, a pattern is defined by, for example, a dry etching in order to leave only a predetetermined polysilicon layer 5a (wiring layer) and 5b (gate electrode) as shown in FIG. 5E. At this time, the P type silicon substrate 1 is also etched by patterning to form a recessed part 4a as shown in the figure. The recessed part 4a in the figure is exaggerated to facilitate the understanding as said in the above. Also, 4b in the figure is a connecting region of the polysilicon layer 5a and the P type silicon substrate 1 (that is, an N.sup.+ type diffusion region which will be described later).
Next, as shown in FIG. 5F, the gate oxide film 3 is a predetermined region is etched away except directly below the polysilicon layer 5b, using the above photoresist 40.
Next, a predetermined area is selectively ion implanted with an N type impurity (for example As) 50 and is annealed (thermal treatment) to form N.sup.+ type diffusion region 6 and 7 (source region and drain region) as shown in FIG. 5G; and furthermore, an interlevel insulating layer 8 (a phosphorus glass film such as, for example, PSG (Phosphosilicate Glass or BPG (Borophosphosilicate Glass) is deposited as shown in FIG. 5H.
Below are the problems which are found after variously examining devices obtained by the fabrication process described in the above.
(1) As shown in FIGS. 5G and 5H, in addition to the above recessed part 4a, the above connecting area 4b in the contact part 4 requires a predetermined region (area) in order to secure connection characteristic of the polysilicon layer (wiring layer) 5a and the N.sup.+ type diffusion region (source region) 6. Therefore, device size reduction has naturally a limit, which is disadvantageous to high degree of integration. PA1 (2) With regard to the above FIG. 5B, when the gate oxide film 3 in the predetermined region (the contact part 4 in FIG. 5C) is removed, the other region (where a gate electrode 5b will be formed later) covered with the photoresist 30 as shown in the figure; and because this photoresist 30 is an organic substance, it also contaminates the gate oxide film 3 in the region which should form the gate electrode 5b (this will significantly lower the reliability of devices). Therefore, the gate oxide film 3 needs to be cleaned in the state shown in FIG. 5C by using various cleaning methods, which will also be very disadvantageous in the process. PA1 (3) Furthermore, with regard to the above FIG. 5C, in the contact part 4 with the gate oxide film 3 in the predetermined area being etched away, a natural oxide film is formed because the below lying P type silicon substrate 1 is exposed. In order to stabilize the connecting characteristic of the P type silicon substrate 1 and the polysilicon layer 5 deposited later in FIG. 5D, the above natural oxide film has to be removed by a wet etching or the like with a water solution of, for example, HF (hydrogen fluoride) or the like, just before the polysilicon layer 5 is deposited (this will be, of course, disadvantageous in the process like the above (1)). However, when the natural oxide layer is etched away, the gate oxide film 3 is also etched; and the thickness of the gate oxide film 3 on which the gate electrode 5b should be formed becomes uneven, so that the reliability of the devices is significantly lowered. PA1 (4) As described in the above, in a mask process of the photoresist 40 or the like in FIG. 5E, the contact part 4 has to have a given excess region (area), when considering a contact part 4 wider than the contact area of the polysilicon layer 5a, or an alignment difference, or the like. For example, if the P type silicon substrate 1 is exposed by the above alignment difference or the like, a dry etching or the like etches also the underlying P type silicon substrate 1 (the recessed part 4a), which significantly lowers the reliability of the devices.
A purpose of the invention is to provide semiconductor devices which are highly reliable and permit high degrees of integration, and a fabrication method thereof.